Instruction Prediction for Step Power Reduction

.4bstractBecause the inductive noise L d i l d t is induced by the power change and can have disastrous impact on the timing and reliability of the system, high-performance CPU designs are more concerned with the step power reduction instead of the average power reduction. The step power is defined as the power difference between the previous and present clock cycles, and represents the L d i l d t noise at the microarchitecture level. Two mechanisms at the microarchitecture level are proposed in this paper to reduce the step power of the floating point unit (FPU) , as F P U is the potential “hot” spot of L d i l d t noise. The two mechanisms, ramping up and ramping down F P U based on instruction fetch queue (IFQ) scanning and PC + N instruction prediction, can meet any specific s t ep power constraint. We implement and evaluate the two mechanisms using a performance and power simulator based on the SimpleScalar toolset. Experiments using SPEC95 benchmarks show that our method reduces the performance loss by a factor of four when compared to a recent work.